module risk_detect (
    input wire [4:0] rR1_ID,
    input wire [4:0] rR2_ID,
    input wire [4:0] wR_EX,
    input wire [4:0] wR_MEM,
    input wire [4:0] wR_WB,
    input wire rf_we_EX,
    input wire rf_we_MEM,
    input wire rf_we_WB,
    input wire pc_op_EX,

    output wire pause_PC,
    output wire pause_IF_ID,
    output wire pause_ID_EX,
    output wire pause_EX_MEM,
    output wire pause_MEM_WB,
    output wire flush_IF_ID,
    output wire flush_ID_EX,
    output wire flush_EX_MEM,
    output wire flush_MEM_WB
);

wire data_risk1_rd1 = (wR_WB == rR1_ID) & rf_we_WB & (wR_WB != 5'b0);
wire data_risk1_rd2 = (wR_WB == rR2_ID) & rf_we_WB & (wR_WB != 5'b0);
wire data_risk2_rd1 = (wR_MEM == rR1_ID) & rf_we_MEM & (wR_MEM != 5'b0);
wire data_risk2_rd2 = (wR_MEM == rR2_ID) & rf_we_MEM & (wR_MEM != 5'b0);
wire data_risk3_rd1 = (wR_EX == rR1_ID) & rf_we_EX & (wR_EX != 5'b0);
wire data_risk3_rd2 = (wR_EX == rR2_ID) & rf_we_EX & (wR_EX != 5'b0);

wire data_risk1 = data_risk1_rd1 | data_risk1_rd2;
wire data_risk2 = data_risk2_rd1 | data_risk2_rd2;
wire data_risk3 = data_risk3_rd1 | data_risk3_rd2;
wire data_risk = data_risk1 | data_risk2 | data_risk3;
wire control_risk = pc_op_EX;

assign pause_PC = data_risk;
assign pause_IF_ID = data_risk;
assign pause_ID_EX = 1'b0;
assign pause_EX_MEM = 1'b0;
assign pause_MEM_WB = 1'b0;

assign flush_IF_ID = control_risk;
assign flush_ID_EX = data_risk | control_risk;
assign flush_EX_MEM = 1'b0;
assign flush_MEM_WB = 1'b0;


endmodule